There has been more demands recently to further increase the operation speeds of semiconductor devices, and the current mirror amplifier circuit is used as one means of realizing the high-speed operation. However, there is now a demand to increase the operation speed of the current mirror amplifier circuit.
Conventionally, in the current mirror amplifier circuit, it is desirable that a pair of nodes from which differentially amplified signals are obtained is set to the same level in a standby mode. If the levels of the nodes were different in the standby mode, the time it takes for the levels of the nodes to reach a threshold voltage of a circuit which is provided in a next stage becomes different depending on whether the signal level rises or falls when the operation of the current mirror amplifier circuit starts from the standby mode, thereby causing a delay in the operation of the current mirror amplifier circuit.
Accordingly, there is a proposed current mirror amplifier circuit in which the pair of nodes from which the differentially amplified signals are obtained is set to the same level in the standby mode. FIG. 1 shows this proposed current mirror amplifier circuit. In FIG. 1, sources of N-channel MOS transistors (hereinafter simply referred to as NMOS transistors) T1 and T2 are coupled to form a differential amplifier circuit part. The sources of the NMOS transistors T1 and T2 are coupled to ground GND via an NMOS transistor T3 which forms a switching circuit part. On the other hand, a drain of the NMOS transistor T1 is coupled to a power source Vcc via a P-channel MOS transistor (hereinafter simply referred to as a PMOS transistor) T4, and a drain of the NMOS transistor T2 is coupled to the power source Vcc via a PMOS transistor T5. Gates of the PMOS transistors T4 and T5 are connected in common to a node B which is connected to a drain of the PMOS transistor T5.
A PMOS transistor T6 is coupled in parallel to the PMOS transistor T4, and a PMOS transistor T7 is coupled in parallel to the PMOS transistor T5. An activation signal .phi. which is applied to a gate of the NMOS transistor T3 is also applied to gates of the PMOS transistors T6 and T7.
In the standby mode in which no activation signal .phi. is received by the current mirror amplifier circuit, a zero voltage is applied to the gates of the PMOS transistors T6 and T7 and the NMOS transistor T3. Accordingly, the NMOS transistor T3 is OFF and the PMOS transistors T6 and T7 are ON. In addition, the potentials at the nodes A and B from which output signals V.sub.OUT and V.sub.OUT are respectively obtained are set to the same level, that is, the power source voltage Vcc.
When the activation signal .phi. is received in this state, the power source voltage Vcc is applied to the gates of the PMOS transistors T6 and T7 and the NMOS transistor T3. Hence, the PMOS transistors T6 and T7 turn OFF and the NMOS transistor T3 turns ON. As a result, the potentials at the nodes A and B both begin to fall. The PMOS transistors T4 and T5 turn ON when the potential at the node B falls to a level which is a threshold voltage Vth of the PMOS transistor T5 lower than the power source voltage Vcc.
If a signal V.sub.IN applied to a gate of the NMOS transistor T1 is lower than a signal V.sub.IN which is applied to a gate of the NMOS transistor T2, the potential at the node A increases towards the high potential side while the potential at the node B decreases towards the low potential side, as shown in FIG. 2. In other words, the potentials at the nodes A and B are differentially amplified.
Because the potentials at the nodes A and B of the current mirror amplifier circuit shown in FIG. 1 are set to the same level in the standby mode, the rise and fall times of the output signals V.sub.OUT and V.sub.OUT output via the nodes A and B required to reach the threshold voltage of the circuit provided in the next stage are constant when the operation of the current mirror amplifier circuit is started from the standby mode. In other words, the time it takes for the potentials at the nodes A and B to reach the threshold voltage of the circuit which is provided in the next stage becomes constant, thereby preventing a delay in the operation of the current mirror amplifier circuit.
In addition, according to the current mirror amplifier circuit shown in FIG. 1, the PMOS transistors T6 and T7 are ON in the standby mode and the potentials at the nodes A and B are set to the same power source voltage Vcc. For this reason, the potentials at the nodes A and B will not become higher than the power source voltage Vcc even if the power source voltage Vcc fluctuates due to noise or the like and the nodes A and B assume floating states. Further, since a symmetrical circuit construction is realized by coupling the PMOS transistors T6 and T6 in parallel with the corresponding PMOS transistors T4 and T5, the pattern design of the current mirror amplifier circuit is facilitated and a fine electrical characteristic is obtained.
However, when the current mirror amplifier circuit shown in FIG. 1 receives the activation signal .phi., no current path exists from the power source Vcc to the ground GND because the PMOS transistors T6 and T7 turn OFF. In other words, the potentials at the nodes A and B fall by discharge. But when the potential fall at the node B to a voltage which is the threshold voltage Vth lower than the power source voltage Vcc for the purpose of turning ON the PMOS transistors T4 and T5 depends on the discharge, the potential fall takes time and there is a problem in that the operation speed of the current mirror amplifier circuit cannot be further improved.